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In applications using large amounts of data, hiding the latency
inherent in accessing data far from the processor is often necessary
in order to achieve high performance. Several researchers have
observed that one way to address the challenge of latency is by using
a common structure: in a series of passes, the program reads in the
data, performs various operations on it, and writes out the data.
Passes often consist of a pipeline structure composed of different
stages. In order to achieve high performance, the stages are
frequently overlapped, for example, by using asynchronous threads.
Out-of-core parallel programs provide one such example of this
pattern. The development and debugging time resulting from
coordinating overlapping stages, however, can be substantial.
Moreover, modifying the structure of the overlap in an attempt to
achieve higher performance can require significant additional time on
the part of the programmer. This thesis presents FG, a Framework
Generator designed to coordinate the stages of a pipeline and allow
the programmer to easily experiment with the pipeline's structure,
thus significantly reducing time to solution. We also discuss
preliminary results of using FG in an out-of-core sorting program.
Bibliographic citation for this report: [plain text] [BIB] [BibTeX] [Refer]
Or copy and paste:
Elizabeth A. Hamon, "Enhancing Asynchronous Parallel Computing." Dartmouth Computer Science Technical Report TR2003-460, June 2003.
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