@Article{batcher:staran,
  author = {K. E. Batcher},
  title = {{STARAN} Parallel Processor System Hardware},
  journal = {AFIPS Conference Proceedings},
  year = {1974},
  pages = {405--410},
  keywords = {parallel architecture, array processor, parallel I/O, SIMD,
  pario-bib},
  comment = {This paper is reproduced in Kuhn and Padua's (1981, IEEE) survey
  ``Tutorial on Parallel Processing.'' The STARAN is an array processor that
  uses Multi-Dimensional-Access (MDA) memories and permutation networks to
  access data in bit slices in a variety of ways, with high-speed I/O
  capabilities. Its router (called the {\em flip} network) could permute data
  among the array processors, or between the array processors and external
  devices, including disks, video input, and displays.}
}