@InProceedings{duzett:ncube3,
  author = {Bob Duzett and Ron Buck},
  title = {An Overview of the {nCUBE~3} Supercomputer},
  booktitle = {Proceedings of the Fourth Symposium on the Frontiers of
  Massively Parallel Computation},
  year = {1992},
  pages = {458--464},
  keywords = {parallel computer architecture, MIMD, pario-bib},
  comment = {Basically the same architecture as the nCUBE/2, scaled up. Eight
  to 65K processors, each 50 MIPS and 100 DP MFLOPS, initially 50 MHz. RISC. 16
  hypercube channels and 2 I/O channels per processor. CPU chip includes MMU,
  TLB, I- and D-cache, hypercube and I/O channels, and memory interface. The
  channels have DMA support built-in (5 usec startup overhead, worst-case
  end-to-end latency 10 usec), and can talk directly to the memory interface or
  to the cache. 64-bit virtual address space, with 48 bits implemented.
  Hardware support for distributed virtual memory. Separate 16-node hypercube
  is used for I/O processing, with up to 400 disks attached. Packaging includes
  multi-chip module with DRAMs stacked directly on the CPU chip, fluid-cooled,
  so that an entire node is one package, with the 18 network links as
  essentially its only external connections.}
}