@TechReport{esser:paragon,
  author = {R\"udiger Esser and Renate Knecht},
  title = {{Intel Paragon XP/S} --- Architecture and Software Environment},
  year = {1993},
  month = {April 26},
  number = {KFA-ZAM-IB-9305},
  institution = {Central Institute for Applied Mathematics, Research Center
  J\"ulich, Germany},
  address = {\verb+r.esser@kfa-juelich.de+},
  keywords = {multiprocessor architecture, pario-bib},
  comment = {A nice summary of the Paragon architecture and OS. Some
  information that is not found in Intel's technical summary, and with much
  less marketing hype. But, it was written in April 1993 with a look to the
  future, so it may represent things that are not ready yet. Network interface
  allows user-mode msgs, DMA direct to user space if receive has been posted;
  else there is a new queue for every possible sending processor. They plan to
  expand the nodes to 4-processors and 64-128 MB. PFS stripes across RAIDs. Now
  SCSI-1 with 5 MB/s, later 10 MB/s SCSI-2, then 20 MB/s fast SCSI-2. See also
  intel:paragon.}
}